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TM
HD-4702/883
CMOS Programmable Bit Rate Generator
Description
The HD-4702/883 Bit Rate Generator provides the necessary clock signals for digital data transmission systems, such as a UART. It generates 13 commonly used bit rates using an on-chip crystal oscillator or an external input. For conventional operation generating 16 output clock pulses per bit period, the input clock frequency must be 2.4576MHz (i.e., 9600 Baud x 16 x 16, since there is an internal / 16 prescaler). A lower input frequency will result in a proportionally lower output frequency. The HD-4702/883 can provide multi-channel operation with a minimum of external logic by having the clock frequency CO and the / 8 prescaler outputs Q0 , Q1 , Q2 available externally. All signals have a 50% duty cycle except 1800 Baud, which has less than 0.39% distortion. The four rate select inputs (S0-S3) select which bit rate is at the output (Z). See Truth Table for Rate Select Inputs for select code and output bit rate. Two of the 16 select codes for the HD-4702/883 do not select an internally generated frequency, but select an input into which the user can feed either a different frequency, or a static level (High or Low) to generate "ZERO BAUD". The bit rates most commonly used in modern data terminals (110,150, 300,1200, 2400 Baud) require that no more than one input be grounded for the HD-4702/883, which is easily achieved with a single 5-position switch. The HD-4702/883 has an initialization circuit which generates a master reset for the scan counter. This signal is derived from a digital differentiator that senses the first high level on the CP input after the ECP input goes low. When ECP is high, selecting the crystal input, CP must be low. A high level on CP would apply a continuous reset. See Clock Modes and Initialization below.
June 1998
Features
* This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1. 2. 1. * HD-4702/883 Provides 13 Commonly Used Bit Rates * Uses a 2.4576MHz Crystal/Input for Standard Frequency Output (16 Times Bit Rate) * Low Power Dissipation * Conforms to ElA RS-404 * One HD-4702/883 Controls up to Eight Transmission Channels * Initialization Circuit Facilitates Diagnostic Fault Isolation * On-Chip Input Pull-Up Circuit
Ordering Information
PART NUMBER HD1-4702/883 TEMPERATURE RANGE (oC) -55 to 125 PACKAGE CERDIP PKG. NO. F16.3
Pinout
HD-4702/883 (CERDIP) TOP VIEW
Q0 Q1 Q2 ECP CP OX IX GND 1 2 3 4 5 6 7 8 16 VCC 15 IM 14 S0 13 S1 12 S2 11 S3 10 Z 9 CO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
FN2955.2
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HD-4702/883 Truth Table
TRUTH TABLE FOR RATE SELECT INPUTS (Using 2.4576MHz Crystal) IX S3 L L L L L L L L H H H H H H H H NOTE: 1. 19200 Baud by connecting Q2 to IM . S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H OUTPUT RATE (Z) MUX Input (lM) MUX Input (lM) X 50 Baud 75 Baud 134.5 Baud 200 Baud 600 Baud 2400 Baud 9600 Baud 4800 Baud 1800 Baud 1200 Baud 2400 Baud 300 Baud 150 Baud 110 Baud X X NOTE: 2. Actual output frequency is 16 times the indicated output rate, assuming a clock frequency of 2.4576MHz. H L X = HIGH Level = LOW Level = Don't Care = Clock Pulse = First HIGH Level Clock Pulse after ECP goes LOW H L H L Clocked from CP Continuous Reset Reset During First CP = High Time H L Clocked from IX CLOCK MODES AND INITIALIZATION ECP CP OPERATION
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HD-4702/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Typical Derating Factor . . . . . . . . . . . 1mA/MHz Increase in ICCOP
Thermal Information
Thermal Resistance, (Typical, Note 3) CERDIP Package . . . . . . . . . . . . . .
JA (oC/W) JC (oC/W)
78 23
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . . . -55oC to 125oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3
DC PARAMETER Input High Voltage Input Low Voltage Output High Voltage
SYMBOL VIH VIL VOH1 VOL1
CONDITIONS VCC = 4.5V VCC = 4.5V IOH -1A, VCC = 4.5V, (Note 4) IOL +1A, VCC = 4 5V, (Note 4) VIN = VCC . All Other Pins = 0V, VCC = 5.5V VIN = 0V, All Other Pins = VCC , VCC = 5.5V VIN = 0V All Other Pins = VCC , VCC = 5.5V (Note 5) VOUT = VCC -0.5, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table VOUT = 2.5V, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table VOUT = VCC -0.5, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table VOUT = 0.4V, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table VOUT = 0.4V, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table
TEMPERATURE ( oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125
MIN VCC 70% V CC -0.1 -
MAX VCC 30% -
UNITS V V V
Output Low Voltage
1, 2, 3
0.1
V A A A
Input High Current
IIH
1, 2, 3
-1
+1
Input Low Current (IX Input) Input Low Current (All Other Inputs) Output High Current (OX)
IILX
1, 2, 3
-1
+1
IlL IOHX
1, 2, 3
-
-100
1, 2, 3
-0.1
-
mA
Output High Current (All Other Outputs)
IOH1
1, 2, 3
-55 TA 125
-1.0
-
mA
Output High Current (All Other Outputs)
IOH2
1, 2, 3
-55 TA 125
-0.3
-
mA
Output Low Current (OX)
IOLX
1, 2, 3
-55 TA 125
0.1
-
mA
Output Low Current (All Other Outputs)
IOL
1, 2, 3
-55 TA 125
1.6
-
mA
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HD-4702/883
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested GROUP A SUBGROUPS 1, 2, 3
DC PARAMETER Supply Current (Static)
SYMBOL ICC
CONDITIONS ECP = VCC , CP = 0V, VCC = 5.5V All Other Inputs = GND, (Note 5) ECP = VCC , CP = 0V, VCC = 5.5V All Other Inputs = VCC (Note 5)
TEMPERATURE ( oC) -55 TA 125
MIN -
MAX 1500
UNITS A
1, 2, 3
-55 TA 125
-
1000
A
NOTES: 4. Interchanging of force and sense conditions is permitted. 5. Input Current and Quiescent Power Supply Current are relatively higher for this device because of active pull-up circuits on all inputs except IX . TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested. AC PARAMETER Propagation Delay, IX to C O Propagation Delay, IX to C O Propagation Delay, CP to CO Propagation Delay, CP to CO Propagation Delay, CO to Q n Propagation Delay, CO to Qn Propagation Delay, CO to Z Propagation Delay, CO to Z Output Transition Time (Except O X) Output Transition Time (Except O X) Set-UpTime Select to CO Hold Time, Select to C O Set-UpTime, IM to CO Hold Time, IM to CO Minimum Clock Pulse Width, Low (Notes 8, 9) Minimum Clock Pulse Width, High (Notes 8, 9) Minimum IX Pulse Width, Low (Note 9) Minimum IX Pulse Width, High (Note 9) NOTES: 6. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (CL). Set-Up Times (tS), Hold Times (tH), and Minimum Pulse Widths (tW) do not vary with load capacitance. 7. For multichannel operation, Propagation Delay (CO to Qn), plus Set-Up Time, Select to CO , is guaranteed to be 367ns. 8. The first High Level Clock Pulse alter ECP goes Low must be at least 350ns long to guarantee reset of all Counters. 9. It is recommended that input rise and fall times to the clock inputs (CP , IX) be less than 15ns. SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS tH tS tH tWCP(L) tWCP(H) tWCP(L) tWCP(H) VCC = 4.5V CL 7pF on OX CL = 50pF (Note 6) CONDITIONS GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 350 0 350 0 120 120 160 160 MIN MAX 350 275 260 220 (Note 7) (Note 7) 85 75 160 75 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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HD-4702/883
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS AC PARAMETER Input Capacitance Output Capacitance SYMBOL CIN CO CONDITIONS All Measurements are referenced to device ground, f = 1MHz. NOTES TEMPERATURE (oC) 10 10 TA = 25 TA = 25 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN MAX 7.0 15.0 UNITS pF pF
Propagation Delay IX to CO Propagation Delay IX to CO Propagation Delay CP to CO Propagation Delay CP to CO Propagation Delay CO to Qn Propagation Delay CO to Qn Propagation Delay CO to Z Propagation Delay CO to Z Output Transition Time (Except OX) Output Transition Time (Except OX) NOTES:
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL VCC = 4.5V C L 7pF on OX C L = 15pF
10, 12 10, 12 10, 12 10, 12 10, 12 10, 12 10, 12 10, 12 10, 12 10, 12
-
300 250 215 195 (Note 11) (Note 11) 75 65 80 40
ns ns ns ns ns ns ns ns ns ns
10. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 11. For multichannel operation, Propagation Delay (CO to Qn) plus Set-Up Time, Select to CO , is guaranteed to be 367ns. 12. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (CL). Set-Up Times (tS), Hold Times (tH), and Minimum Pulse Widths (tW) do not vary with load capacitance.
TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
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HD-4702/883 Burn-In Circuit
HD-4702/883 CERDIP
VCC C1 R1 VCC/2 VCC/2 VCC/2 GND R1 F0 R1 VCC/2 GND GND 6 R1 7 8 10 R1 9 11 R1 VCC/2 VCC/2 1 R1 2 R1 3 R1 4 5 13 R1 12 R1 F15 F14 14 R1 F13 15 R1 F12 16 R1 F4
NOTES: 13. F0 = 100kHz 10%, F1 = F0/2, F2 = F1/2., ... 14. R1 = 10k, 1/4W, 10%. 15. V CC = 5.5V 0.5V, GND = 0V. 16. C1 = 0.01F Min.
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HD-4702/883 Die Characteristics
DIE DIMENSIONS: 100 mils x 97 mils x 19 mils METALLIZATION: Type: Si - AI Thickness: 10kA - 12kA GLASSIVATION: Type: SiO2 Thickness: 7kA - 9kA WORST CASE CURRENT DENSITY: 7.1 x 104A/cm 2
Metallization Mask Layout
HD-4702/883
Q0
VCC
IM
Q1
S0
S1
Q2
ECP
S2
CP OX IX GND CO Z
S3
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HD-4702/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
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